1. Field of the Invention
The present invention relates in general to integrated circuit crosspoint switches and in particular to a crosspoint switch having switch cells employing active tristate buffers.
2. Description of Related Art
An Nxc3x97M crosspoint switch, such as disclosed for example in U.S. Pat. No. 5,790,048 issued Aug. 4, 1998 to Hsieh et al, employs an array of pass transistors to selectively route input signals arriving at any of N input ports to any of M output ports.
FIG. 1 illustrates a simplified example 4xc3x974 crosspoint switch 10 as might be implemented in an integrated circuit. Crosspoint switch 10 includes a set of four input signal drivers D0-D3 acting as input ports, a set of four receivers R0-R3 acting as output ports, a switch cell array 12 for selectively providing signal paths between drivers D0-D3 and receivers R0-R3, and an array controller 14. Crosspoint array 12 includes four rows and four columns of switch cells 16. Each of four conductive input lines H0-H3 lines deliver the output of a separate one of drivers D0-D3 to a separate row of switch cells 16. Each of four conductive output lines V0-V3 lines link a separate column of switch cells 16 to an input of a separate one of receivers R0-R3. Each switch cell 16 can selectively provide a signal path between one of input lines H0-H3 and one of output lines V0-V3. A controller 14 writes single bit control data into a memory cell within in each switch cell 16, and the state of the bit determines whether or not the cell is to provide the signal path. Commands arriving on a control bus 22 from an external source such as a host computer tell controller 14 how to set the states of bits stored in the various switch cells 16.
When, for example, driver D0 receives input signal IN(0) arriving at one of switch input terminals 18, it buffers them onto its corresponding input line H0. Each one of the four switch cells 16 that are linked to input line H0, and which happen to be configured by their stored data bit to provide a signal path, then forwards the signal to one of receivers R0-R3 via its corresponding output line V0-V3. Each receiver R0-R3 that receives the signal then buffers the signal onto one of four switch output terminals 20 as one of output signals OUT(0)-OUT(3).
FIG. 2 illustrates a portion of the prior art crosspoint switch 10 of FIG. 1 in more detail, including driver D0, input line H0, output lines V0-V3, the four cells 16 linking input line H0 to output lines V0-V3 and receivers R0-R3. FIG. 2 also shows driver D0 and receivers R0-R3 of FIG. 1. Each switch cell 16 includes a pass transistor Q having its source terminal connected to input line H0 and its drain terminal connected to one of output lines V0-V3. Each switch cell 16 also includes a memory cell 25 for storing the control bit from controller 14. Controller 14 of FIG. 1 uses a control bus 24 to separately write a bit into the memory cell 25 of each switch cell 16, and that control bit drives the gate of transistor Q. Pass transistor Q of each cell 16 passes signals from input line HO to one of output lines V0-V3 when the bit in memory cell 25 turns the pass transistor on and blocks a signal on line H0 from passing to that output line when the bit turns the pass transistor off.
Although for simplicity array 12 is illustrated as a 4xc3x974 switch cell array, switch cell arrays of similar design can be made much larger to provide flexible routing paths between much larger numbers of input and output ports. Regardless of the dimensions of crosspoint switch 10, we would like the crosspoint switch to route signals with as little delay and distortion as possible. However, crosspoint switch 10 can exhibit significant signal path delay and distortion, both of which can increase as we increase the Nxc3x97M dimensions of array 12.
Referring to FIG. 2, assume that the pass transistor Q of the switch cell 16 linking input line H0 to output line V0 is on and that the pass transistors Q of all other switch cells 16 are off. When the input signal IN(0) to driver D0 changes state, the output signal OUT(0) produced by driver R0 will also change state with a time delay that is the sum of the inherent delays of driver D0 and receiver R0 and the signal path delay through switch cell array 12. The signal path delay arises primarily because the output signal produced by driver D0 on line H0 must charge or discharge all of the shunt capacitance linked to the input and output lines V0 and H0 before it can force receiver R0 to drive OUT(0) to another state. That shunt capacitance includes not only the inherent capacitance of the lines and the input capacitance of the receiver R0, it also includes capacitance associated with the pass transistor, Q linked to both input line H0 and output line V0, capacitances associated with the pass transistors Q of the three other switch cells 16 that are also connected to input line H0 and the three other transistors Q connected to vertical line V0.
When we increase the size of the array, for example from 4xc3x974 to 8xc3x978, then each input and output line H0 and V0 will now be connected to eight cells, rather than four. Thus driver D0 will have to charge or discharge the capacitances associated with fifteen transistors rather than seven and input capacitances of up to eight receivers instead of four. Since increasing the size of array 12 increases the capacitance linked to its input and output lines, and since signal delay increases with capacitance, we lengthen the signal path delay when we increase array size.
A driver charges a capacitor at a rate in inverse relation to the product of its capacitance and the series resistance between the driver""s voltage source and the capacitor. Thus one way to reduce the signal path delay through array 12 is to increase the size of drivers D0-D3 (i.e., reduce their output resistance) so that they conduct more current when charging and discharging capacitance. This reduces the time the drivers need to charge or discharge the capacitance of array 12, thereby reducing signal path delay. However since there are practical limits to the size of a driver we can incorporate into an integrated circuit, we would like to provide another way to reduce signal path delay.
We could reduce signal path delay by reducing the capacitance of pass transistors Q by making them smaller. However since smaller pass transistors have higher resistance, the gain in speed resulting from reduced capacitance can be offset by the increased resistance. Therefore while we can attain some delay reduction by optimizing the tradeoff between the capacitance and resistance of pass transistors Q, there are limits to this approach as well. Therefore it would beneficial to provide yet another way to attain further reductions in signal path delay through array 12.
Signal distortion can be problematic in crosspoint switch 10. In crosspoint switches implemented using metal oxide semiconductor field effect transistors (MOSFETs), pass transistor Q is typically an n-channel metal oxide semiconductor (nMOS) transistor because nMOS transistors normally have lower capacitance than p-channel metal oxide semiconductor (pMOS) transistors of similar size. However since an nMOS transistor""s impedance is not symmetric with respect to the direction of its channel current, transistors Q of FIG. 2 charge and discharge capacitance at different rates. Signal path delay is therefore a function of whether an input signal IN(0)-IN(3) is rising or falling. This lack of symmetry results in what is known as xe2x80x9cduty cyclexe2x80x9d distortion in the OUT(0)-OUT(3) signals wherein rise and fall times of leading and trailing edges are not symmetric. Since increasing the amount of capacitance that drivers D0-D3 must charge and discharge can increase duty cycle distortion, we also increase duty cycle distortion when we increase the Nxc3x97M dimensions of the crosspoint switch.
What is needed is an architecture for a large crosspoint switch that helps reduce duty cycle distortion and signal path delay.
A high-speed, low distortion Nxc3x97M crosspoint switch selectively routes input signals arriving at any of N input terminals to one or more of M output terminals. The crosspoint switch includes a switch cell array having N rows and M columns of switch cells. Each of N input lines convey at a separate one of the N input signals to each switch cell of a corresponding array row. Each of M output lines convey output signals generated by cells of a corresponding array column to a separate switch output terminal.
In accordance with one aspect of the invention, each switch cell contains a tristate buffer and a memory cell for storing data controlling whether the tristate buffer is active or inactive. When the tristate buffer is active, it buffers an input signal received on the its input line to generate an output signal on its output line. When inactive, the tristate buffer refrains from generating an output signal in response to its input signal. Unlike the pass transistors used in prior art switch cell arrays, the tristate buffers actively charge and discharge capacitance of the array""s output lines, thereby helping to reduce the signal path delay through the array by providing increased charging currents.
In accordance with another aspect of the invention, the tristate buffers are implemented as complementary metal oxide semiconductor (CMOS) circuits. In comparison to nMOS pass transistors employed in prior art crosspoint switch arrays, CMOS tristate buffers produce less duty cycle distortion in the crosspoint switch""s output signals because they can provide relatively symmetric leading and trailing edges in their output signals.
In accordance with a further aspect of the invention, each tristate buffer incorporates CMOS pass gates at its input for decoupling its load transistors from its input line when the tristate buffer is inactive. Since the pass gate de-couples most of the capacitance of the tristate buffer from the switch input line when the buffer is not active, it helps to further reduce signal path delays through the switch array, particularly when the switch cell array is relatively large.
It is accordingly an object of the invention to provide a large, high-speed, low-distortion, crosspoint switch.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.